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the information in this document is subject to change without notice. ? 1998 240 output lcd column ( segment ) driver with built-in ram mos integrated circuit m m m m pd16662 data sheet document no. s12738ej3v0ds00 (3rd edition) date published november 1998 ns cp (k) printed in japan the mark ? ? ? ? shows major revised points. the m pd16662 is a column (segment) driver which contains a ram capable of full dot lcd drive. with 240 outputs, this driver has a display ram of 240 x 160 x 2 bits built in, and 4 gray scales of display are possible. any 4 gray scales can be selected from 25 levels of the gray scale pallet. the driver can be combined with the m pd16667 to display from 240 x 160 dots to 480 x 320 dots. features display ram incorporated: 240 x 160 x 2 bits logic voltage: 3.0v to 3.6v duty: 1/160 output count: 240 outputs capable of gray scale display: 4 gray scales (can be selected from 25 levels of the gray scale pallet) memory management: packed pixel system 8/16-bit data base ordering information part number package m pd16662n - tcp(tab) m pd16662n - 051 standard tcp (olb: 0.2 mm pitch; folding) the tcps external shape is custom-ordered. therefore, if you have a shape in mind, please contact an nec salesperson. ?
2 m m m m pd 16662 pin name classification voltage pin name note i/o function cpu i/f 3.3 v d0 to d15 a0 to a16 /cs /oe /we /ube rdy i/o i i i i i o data bus 16 address bus 17 chip select read signal write signal high byte enable ready signal to cpu (ready state at h) control signals 3.3 v pl0 pl1 dir ms bmode /refrh test /reset /doff osc1 osc2 i i i i i i/o i i i - - specifies the lsi allocation locations (no. 0 to 3). specifies the lsi allocation locations (no. 0 to 3). specifies the liquid-crystal panel allocation direction (longitudinal; lateral) master/slave switching (master mode at h) data bus bit select pin ("h" = 8bit, "l" = 16bit) self diagnostic reset pin (wired or connection) test pin (test mode at h, using the pull-down buffer) reset display off signal input oscillator pin oscillator pin 5.0 v stb /frm pulse l1 l2 /dout i/o i/o i/o i/o i/o o column driving signal strobe (ms signal "h" = output, ms signal "l" = input ) frame signal(ms pin "h" = output , ms pin "l" = input ) 25-gray level pulse modulation clock row driver drive level selection signal (1st line) row driver drive level selection signal (2nd line) display off signal output liquid-crystal drive y1 to y240 o liquid-crystal drive output powers gnd v cc1 v cc2 v 0 v 1 v 2 - - - - - - ground (two 5-v pins; three 3-v pins) 5-v power level 3.3-v power level liquid-crystal drive analog power liquid-crystal drive analog power liquid-crystal drive analog power remark /xxx indicates active low signal. note 3.3-v power pins : d0 - d15, a0 - a16, /cs, /oe, /we, /ube, rdy, bmode, pl0, pl1, dir, osc1, osc2, /reset, /doff, test, ms 5-v power pins : stb, /frm, l1, l2, /dout, pulse
3 m m m m pd 16662 block diagram ram 240 x 160 x 2 bit dec liquid crystal drive circuit 240 outputs 3.3 v operation 5.0 v operation 3.3 v operation 5.0 v operation v0 v1 v2 y240 y1 y2 y3 l2 /dout stb /frm pulse l1 pulse /frm stb dir pl0, pl1 test rdy bmode d0 - d15 /refrh /reset ms /doff osc1 osc2 stop a0 - a16 control /cs, /oe, /we, /ube address input control address management control arbiter data latch (1) data latch (2) gray level control gray scale generation circuit internal timing generation self-diagnosis circuit data bus control cr oscillator liquid crystal timing generation level shifter
4 m m m m pd 16662 block functions (1) address management circuit the address management circuit converts addresses transferred from the system through a0 to a16 into addresses compatible with the memory map of the built-in ram. this function can be used to address up to 480 x 320 dots with four of these lsis, thus making it possible to configure a liquid crystal display system without difficulty. moreover, addresses 1fff0h to 1ffffh are allocated to the gray scale pallet register, making it possible to choose any 4 gray scales from the 25-level pallet. (2) arbiter the arbiter adjusts the contention between the ram access from the system and the ram read on the liquid-crystal drive side. (3) ram static ram (single port) of 240 by 160 by 2 bits (4) data bus control this circuit controls the data transfer directions through the read/write from the system. it also performs an 8/16-bit switch via the bmode pin. (5) gray scale generation circuit this circuit realizes the 25 levels by frame thinning out and pulse width modulation. (6) internal timing generation internal timing to each block is generated from /frm and stb signals. (7) cr oscillator the cr oscillator generates the clock which will become a criterion of the frame frequency in master mode. 1/2592 of this oscillation becomes the frame frequency. for example, if the frame frequency is 70 hz, the required oscillation frequency is 181.44 khz. as the cr oscillator has a built-in capacitor, adjust the required oscillation frequency with an external resistor. in slave mode, the oscillation is stopped. (8) liquid crystal timing generation in master mode, /frm (frame signal), stb (column drive signal strobe), and pulse (25-gray-sc ale pallet pulse modulation clock) are generated. (9) gray scale control this circuit realizes a four-gray scale display. (10) data latch (1) reads and latches 240-pixel data from the ram. (11) data latch (2) latches 240-pixel data synchronously with the stb signal.
5 m m m m pd 16662 (12) level shifter the level shifter converts from the operating voltage (3.3 v) of the internal circuit to the liquid-crystal drive circuit and low driver interface voltage (5 v). (13) dec decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages v 0 , v 1 and v 2 . (14) liquid crystal drive circuit this circuit selects one of the liquid-crystal drive powers v 0 , v 1 , and v 2 , which are compatible with the gray scale display data and the display off signal (/doff), to generate the liquid crystal applied voltage. (15) self diagnostic circuit if the operation timing of the master chip and slave chip has deviated due to external noise, this circuit will detect the problem and generate a total column/driver refresh signal. address map image diagram (example of vga-half size configuration) no.0 no.2 no.1 no.3 y240 y240 y1 l1 l160 l1 l160 y1 y240 y240 y1 y1 address progress direction column direction specified with a7 to a0 row direction specified with a16 to a8 address progress direction
6 m m m m pd 16662 data bus the byte data lined up on the data bus is based on the little endian - an nec/intel-series bus. 1. 16 bit data bus (bmode = l) bytes (8 bytes) access d0 to d7 d8 to d15 addresses proceed as shown on right. ? 00000h 00002h 00004h : : : 00001h 00003h 00005h : : : words (16 bits) access d0 to d7 d8 to d15 addresses proceed as shown on right. ? 00000h 00002h 00004h : : : for the access from the system to be performed in units of words (16 bits), or of bytes (8 bytes), the /ube (high byte enable) and a0 are used to show whether valid data are in the bytes of either (or both) of d0 to d7 and d8 to d15. /cs /oe /we /ube a0 mode i/o d0 to d7 d8 to d15 h x x x x not selected hi-z hi-z llhl l h l h l read dout hi-z dout dout dout hi-z lhl l l h l h l write din x din din din x l l h x h x x h x h output disable hi-z hi-z hi-z hi-z remark x : dont care hi-z : high impedance
7 m m m m pd 16662 2. 8 bit data bus (bmode = h) d0 to d7 addresses proceed as shown on right. ? 00000h 00001h 00002h : : : /cs /oe /we mode i/ o d0 to d7 d8 to d15 h x x not selected hi-z note l l h read dout note lhlwritedinnote l h h output disable hi-z note remark x : dont care hi-z : high impedance note use d8 - d15 and /ube to open or connect to the gnd because they are internally pulled down when bmode = h.
8 m m m m pd 16662 relationship between data bits and pixels as the display is in four gray scales, each pixel consists of two bits. the ram is configured with four pixels (8 pixels per word) using the packed pixel system. (1) bmode = l bytes (8 bits) access d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 1 pixel pixel pixel pixel pixel pixel pixel pixel 00000h 00001h 2345678 liquid-crystal panel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 00000h 00001h 00002h 00003h words (16 bits) access 00000h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 1 pixel pixel pixel pixel pixel pixel pixel pixel 2345678 liquid-crystal panel 00000h 00002h 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel (2) bmode = h 00000h 00001h d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 1 pixel pixel pixel pixel pixel pixel pixel pixel 2345678 liquid-crystal panel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 pixel 8 pixel 00000h 00001h 00002h 00003h
9 m m m m pd 16662 gray scale control the m pd16662 gray scale control realizes 25 levels of the gray scale pallet through frame thinning and pulse width modulation. it chooses four gray scales and records them in the gray scale pallet register before use. gray scale pallet register through the use of the gray scale pallet register, four gray scales are pre-selected from 25 levels. the gray scale pallet register is allocated in addresses 1fff0h to 1ffffh, and the relationship between the register and the gray scale data is shown in the following table. the initial values are also allocated as below. the gray scale pallet register can set each column/driver configuration position (no.0 to 3) decided by pl0 and pl1. address configuration position gray scale data (display data) initial value no. dn+1 note dn note 1fff0h no.0 0 0 00000b 1fff1h 0 1 01000b 1fff2h 1 0 10000b 1fff3h 1 1 11000b 1fff4h no.1 0 0 00000b 1fff5h 0 1 01000b 1fff6h 1 0 10000b 1fff7h 1 1 11000b 1fff8h no.2 0 0 00000b 1fff9h 0 1 01000b 1fffah 1 0 10000b 1fffbh 1 1 11000b 1fffch no.3 0 0 00000b 1fffdh 0 1 01000b 1fffeh 1 0 10000b 1ffffh 1 1 11000b note n = 0, 2, 4, 6
10 m m m m pd 16662 relationship between gray scale and gray scale pallet data the relationship between the gray scale and the gray scale pallet data that is set by the gray scale pallet register is as follows. pmode gray scale palette data remark d4 d3 d2 d1 d0 pixel 0 00000off pixel 1 00001 pixel 2 00010 pixel 3 00011 pixel 4 00100 pixel 5 00101 pixel 6 00110 pixel 7 00111 pixel 8 010001/3 pixel 9 01001 pixel 10 01010 pixel 11 01011 pixel 12 01100 pixel 13 01101 pixel 14 01110 pixel 15 01111 pixel 16 100002/3 pixel 17 10001 pixel 18 10010 pixel 19 10011 pixel 20 10100 pixel 21 10101 pixel 22 10110 pixel 23 10111 pixel 24 11000on
11 m m m m pd 16662 lsi arrangement and address management addresses can be managed to allow up to four of these lsis to be used to configure a liquid-crystal display of up to half vga size (320 x 480 dots). up to four of these lsis can be connected on the same bus sharing the /cs, /we, and /oe pins. on the system side, one screen of the liquid crystal display can be treated as one memory area, and it is not necessary to decode for more than one m pd16662. the pl0 and pl1 pins are used to specify lsi no. and to determine the lsi arrangement. the dir pins are used to determine the directions (vertical, horizontal) of the liquid- crystal display. pl1 pl0 lsi no. 00no. 0 01no. 1 10no. 2 11no. 3 1. addresses of the vga half-size horizontally (dir = "0") specified with a16 to a8 row row x1 x160 x1 x160 00000 y1 y240 y1 y240 y240 y1 y240 y1 00100 0003a 0013a 00002 column no.0 column column column 00038 09e3a 09f3a 09e00 09f00 09f38 09f02 0a000 0a100 0a03a 0a13a 0a002 no.1 0a038 13e3a 13f3a 13e00 13f00 13f38 13f02 0003c 0013c 00076 00176 0003e no.2 00074 09e76 09f76 09e3c 09f3c 09f74 09f3e 0a03c 0a13c 0a076 0a176 0a03e no.3 0a074 13e76 13f76 13e3c 13f3c 13f74 13f3e specified with a7 to a0
12 m m m m pd 16662 2. addresses of the vga half-size horizontally (dir = "1") 00000 00100 00002 no.0 09e00 09f00 x160 x1 09f02 0003a 0013a 00038 09e3a 09f3a 09f38 0a000 0a100 0a002 no.1 13e00 13f00 y1 y240 y240 y1 x160 x1 13f02 0a03a 0a13a 0a038 13e3a 13f3a 13f38 0003c 0013c 0003e no.2 09e3c 09f3c 09f3e 00076 00176 00074 09e76 09f76 09f74 0a03c 0a13c 0a03e no.3 13e3c 13f3c y1 y240 y240 y1 13f3e 0a076 0a176 0a074 13e76 13f76 13f74 row column column column column row specified with a16 to a8 specified with a7 to a0
13 m m m m pd 16662 cpu interface 1. function of the rdy (ready) pin the built-in ram is a single-port ram. to prevent contention between the access from the cpu side and the reading by the liquid-crystal drive side, the rdy pin performs a wait operation on the cpu. timing wait ready a0 - a16, /ube /cs /oe, /we rdy hi-z hi-z wait connection of the rdy pin the rdy pin uses a three-state buffer. the rdy pin should be connected to an external pull-up resister. if more than one lsi are used, the rdy pins of each lsi are wired together. cpu ready input rdy column driver rdy column driver pull-up resister v cc2 ?
14 m m m m pd 16662 2. access timing (1) display data read timing a16 - a0 rdy d15 - d0 hi-z hi-z hi-z hi-z dout /ube /cs /oe (2) display data write timing din a16 - a0 rdy hi-z hi-z d15 - d0 /ube /cs /oe (3) gray scale pallet data write timing din a16 - a0 /ube /cs /oe rdy hi-z d4 - d0 ?
15 m m m m pd 16662 liquid-crystal timing generation 1. reset state if the circuit is placed in the reset state, the internal counter is zero-cleared. after cancelling the reset, the display off function operates during the 4-frame cycle even when the /doff pin is at h. 12 display off display on 3456 /reset /frm /dout internal state
16 m m m m pd 16662 2. liquid-crystal timing generating circuit if the circuit is set to master mode when ms = h, the /frm and stb signals are generated timed with a duty ratio 1/160. generates the driver drive voltage selection signals l1 and l2 for the row driver. the /frm is generated twice per frame. the stb is generated 81 times per half a frame; and 162 times per frame. generation of /frm and stb signals stb 81 frame 12 8112 8112 /frm osc1 pluse stb 1 2 generation of l1 and l2 signals stb 1234123412341234 l1 1111111100000000 l2 1010010101011010
17 m m m m pd 16662 self diagnostic function this is a function to check whether the timing of each column/driver has deviated due to external noise. the slave chip compares the l1 and l2 generated internally with the l1 and l2 of the master chip, and when there is discordance, it sends a total column/driver refresh signal. when a refresh signal is received, the internal reset is activated and timing is initialized. in this case, the /refrh = l time and the four frame interval display are turned off. the l1, l2 discordance will be monitored at the rising edge of the frm once every 1/2 frame. initialization initialization discrepancy discrepancy l1 (master) l2 (master) l1 (slave) l2 (slave) /refrh block configuration drawing (slave side) self-diagnosis circuit /reset /refrh l1 l2 internal l1 signal internal l2 signal internal reset
18 m m m m pd 16662 system configuration example an example of configuring a liquid-crystal panel of vga half-size (480 320 dots lengthwise) by using four lsis and two row drivers. each column driver sets the lsi no. with pl0, pl1 pins. the dir pins of each column driver are all set to low level. only one of the column drivers is set to the master; all the others are set to the slave. signals are supplied from the master column driver to the slave column driver and to the row driver. connect a resistor for the oscillator to the osc1 and osc2 pins of the master. leave the osc1 and osc2 pins of the slave open. the signals from the system (d0 through d15, a0 through a16, /cs, /oe, /we, /ube, rdy, /reset, and /doff) are connected to all the column drivers in parallel. connect a pull-up resistor to the rdy signal. the test pin is used to test the lsi. open or connect this pin to gnd when the system is configured. pulse stb /frm osc1 osc2 /dout, /doff ' l1 l2 /refrh y1 y240 160 no.1 y240 y1 y1 y240 y240 y1 160 rdy /doff /reset d0 - d15 a0 - a16 control (/cs, /oe, /we, /ube) slave no.1 slave no.1 slave no.1 master scanning direction scanning direction row driver row driver v cc2 remark the /doff' pin is an input pin of m pd16667.
19 m m m m pd 16662 chip set power-on sequence it is recommended to turn on power in the following sequence: v cc2 ? v cc1 ? input ? v dd , v ee ? v 1 , v 2 be sure to turn on lcd driving power supplies v 1 and v 2 last. 0 s min. 0 s min. 0 s min. 100 ns min. off on on on on on on 4.5 v 3.3 v 3.3 v 0.3 v cc2 off 0 v 0 v off off off off v cc2 v cc1 cpu i/f note1 (a0 - a16, /cs, /oe, /we, /ube, d0 - d15, /doff) /reset v dd note2 v ee note2 v 1 v 2 notes 1. it is possible to input the selected pins (pl0, pl1, dir, ms, and bmode) at the same time as v cc2 . 2. it is not necessary to have v dd and v ee on at the same time. v dd and v ee are the liquid crystal power supply of row driver. caution turn off power to the chip set in the reverse sequence to the turn-on sequence.
20 m m m m pd 16662 example of layout of internal schottky barrier diode of module to reinforce power supply protection (use a schottky barrier diode with vf = 0.5 v max.) v dd v cc1 v 2 v 1 v 0 v ss v ee include the diodes enclosed in the dotted line in the above figure when v 0 is not 0 v (gnd). note v dd and v ee are the liquid crystal power supply of row driver.
21 m m m m pd 16662 electrical specifications 1. absolute maximum ratings (t a = +25 c) parameter symbol rating unit notes supply voltage (1) v cc1 - 0.5 to +6.5 v 1 supply voltage (2) v cc2 - 0.5 to +4.5 v 2 input/output voltage (1) v i/o1 - 0.5 to v cc1 +0.5 v 1 input/output voltage (2) v i/o2 - 0.5 to v cc2 +0.5 v 2 input/output voltage (3) v i/o3 - 0.5 to v cc1 +0.5 v 3, 4 operating temperature t a - 20 to +70 c storage temperature t stg. - 40 to +125 c notes 1. 5 v power signal (/frm, stb, /dout, l1, l2, pulse) 2. 3.3 v power signal (ms, dir, pl0 to pl1, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 to d15, /reset, osc1, osc2, /doff, test, bmode, /refrh) 3. liquid-crystal drive powers (v 0 , v 1 , v 2 , y1 to y240) 4. v 0 < v 1 < v 2 2. recommended operating range (t a = 20 to +70 c, v o = 0 v) parameter symbol min. typ. max. unit notes supply voltage (1) v cc1 4.5 5.0 5.5 v supply voltage (2) v cc2 3.0 3.3 3.6 v input voltage (1) v i1 0v cc1 v1 input voltage (2) v i2 0v cc2 v2 v1 input voltage v 1 v 0 v 2 v v2 input voltage v 2 v 1 v cc1 v external resistance for osc r osc 30 62 90 k w notes 1. 5 v power signal (/frm, stb, l1, l2, pulse) 2. 3.3 v power signal (ms, dir, pl0 to pl1, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 to d15, /reset, osc1, osc2, /doff, test, bmode, /refrh) ?
22 m m m m pd 16662 3. dc characteristics (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v. v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20 to +70 c) parameter symbol min. typ. max. unit remark notes high-level input voltage (1) v cc1 v ih1 0.7 v cc1 v1 low-level input voltage (1) v il1 0.3v cc1 v1 high-level input voltage (2) v cc2 v ih2 0.7 v cc2 v2 low-level input voltage (2) v il2 0.3v cc2 v2 high-level output voltage (1) v ih3 0.8 v cc2 v4 low-level output voltage (1) v il4 0.2v cc2 v4 high-level output voltage (2) v cc1 v oh1 v cc1 - 0.4 v i oh = - 1 ma 3 low-level output voltage (2) v ol1 0.4 v i ol = 2 ma 3 high-level output voltage (3) v oh2 v cc1 - 0.4 v i oh = - 2 ma 1 low-level output voltage (3) v ol3 0.4 v i ol = 4 ma 1, 4 high-level output voltage (3) v cc2 v oh3 v cc2 - 0.4 v i oh = - 1 ma 5 low-level output voltage (3) v ol3 0.4 v i ol = 2 ma 5 input leakage current (1) i i1 10 m a without test pin, v i = v cc2 or gnd input leakage current (2) i i2 10 40 100 m a pull down (test pin ) v i = v cc2 current consumption for display operation (1) v cc1 i mas1 100 m amaster 6 current consumption for display operation (2) v cc2 i mas2 250 m amaster 6 current consumption for display operation (3) v cc1 i slv1 60 m aslave 6 current consumption for display operation (4) v cc2 i slv2 150 m aslave 6 liquid crystal drive output on resistance r on 12k w 7 notes 1. 5 v signal (/frm, stb, l1, l2, pulse) 2. 3.3 v signal (ms, dir, pl0 to pl1, a0 to a16, /cs, /oe, /we, /ube, rdy, d0 to d15, /reset, /doff, test, bmode) 3. /dout pin 4. / refrh pin 5. d0 to 15, rdy, and osc2 pins 6. with the frame frequency at 70 hz without output load and cpu no access (d0 to d15, a0 to a16, /ube = gnd, /cs, /oe, /we = v cc2 ) 7. this refers to the resistance value between a y pin and a v pin (either of v 0 , v 1 and v 2 ) when the load current (i on = 100 m a ) is passed to a pin of y1 to y240.
23 m m m m pd 16662 4. ac characteristics 1 display data transfer timing (1) master mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v. v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20 to +70 c, frame frequency 70 hz (f osc = 181.44 khz), output load: 100 pf) parameter symbol min. typ. max. unit remark stb clock cycle time t cyc 87 16/f osc m s stb high-level width t cwh 43 8/f osc m s stb low-level width t cwl 43 8/f osc m s stb rise time t r 100 ns stb fall time t f 100 ns stb -/frm delay time t psf 20 m s /frm -stb delay time t pfs 20 m s t f t r t cwl t cyc t psf t pfs t pfs t psf t cwh 0.9 v cc1 0.1 v cc1 0.9 v cc1 0.1 v cc1 stb (input) /frm (output)
24 m m m m pd 16662 (2) slave mode (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v. v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20 to +70 c) parameter symbol min. typ. max. unit remark stb clock cycle time t cyc 10 m s stb high-level width t cwh 4 m s stb low-level width t cwl 4 m s stb rise time t r 150 ns stb fall time t f 150 ns /frm setup time t sfr 1 m s /frm hold time t hfr 1 m s t f t r t cwl t cyc t sfr t hfr t hfr t sfr t cwh 0.7 v cc1 0.3 v cc1 0.7 v cc1 0.3 v cc1 stb (input) /frm (output)
25 m m m m pd 16662 (3) items common to the master and slaves (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v. v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20 to +70 c) parameter symbol min. typ. max. unit remark output delay time (l1, l2, /dout) t dout1 50 100 ns without output load output delay time (y1 to y240) t dout2 90 150 ns without output load t dout1 t dout1 t dout2 t dout2 0.9 v cc1 0.9 v cc1 0.9 v 2 0.1 v 2 0.9 v 2 0.1 v 2 stb (output) y1 - y240 l1, l2 /dout
26 m m m m pd 16662 5. ac characteristics 2 graphic access timing (unless otherwise specified, v cc1 = 4.5 to 5.5 v, v cc2 = 3.0 to 3.6 v. v 0 = 0 v, v 1 = 1.4 to 2.0 v, v 2 = 2.8 to 4.0 v, t a = - 20 to +70 c, t r = t f = 5 ns) parameter symbol min. typ. max. unit remark notes /oe, /we recovery time t ry 30 ns address setup time t as 10 ns address hold time t ah 20 ns rdy output delay time t ryr 30 ns cl = 15 pf rdy float time t ryz 30 ns 3 wait state time t ryw 35 ns 1 ready state time (without contention) t ryf1 60 100 ns 1 ready state time (with contention) t ryf2 650 1,200 ns 1 data access time (read cycle) t acs 100 ns 2 data float time (read cycle) t hz 40 ns 3 /cs - /oe time (read cycle) t csoe 10 ns /oe - /cs time (read cycle) t oecs 20 ns write pulse width 1 (write cycle 1) t wp1 50 ns 1 write pulse width 2 (write cycle 2) t wp2 50 ns 1 data setup time (write cycle 1, 2) t dw 20 ns data hold time (write cycle 1, 2) t dh 20 ns /cs - /we time (write cycle 1, 2) t cswe 10 ns /we - /cs time (write cycle 1, 2) t wecs 20 ns reset pulse width t wres 100 ns rdy - /oe time t rdoe -- 4 rdy - /we time t rdwe -- 4 notes 1. load circuit v cc2 1.8 k w 60 pf 1.0 k w 2. load circuit v cc2 1.8 k w 100 pf 1.0 k w 3. load circuit v cc2 1.8 k w 5 pf 1.0 k w 4. the display may be affected if the time from the rising of rdy to /oe or /we is too long. it is recommended that t rdoe and t rdwe be 1,000 ns max. ? ? ? ?
27 m m m m pd 16662 /oe, /we recovery time t ry 0.7 v cc2 0.3 v cc2 /oe, /we read cycle a16 - d0 /ube /cs /oe rdy d15 - d0 hi-z hi-z t as t ah 0.7 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.9 v cc2 0.9 v cc2 0.1 v cc2 t ryf t ryr 0.1 v cc2 0.3 v cc2 t acs t rdoe t ryw t hz out t ryz 0.1 v cc2 t oecs t oecs ?
28 m m m m pd 16662 write cycle 1 (display data write) hi-z t as t ah 0.7 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 t ryf t ryr 0.1 v cc2 0.3 v cc2 t wp t dw t dh t rdwe in t cswe hi-z 0.9 v cc2 t ryw t ryz 0.1 v cc2 t wecs a16 - a0 /ube /cs /we rdy d15 - d0 write cycle 2 (gray scale pallet data write) hi-z t as t ah 0.7 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.7 v cc2 0.3 v cc2 0.3 v cc2 t wp2 t dw t dh in t cswe t wecs a16 - a0 /ube /cs /we rdy d15 - d0 ?
29 m m m m pd 16662 reset pulse width t wres 0.3 v cc2 /reset 6. ac characteristics 3 cr oscillator (v cc2 = 3.0 to 3.6 v, ta = - 20 to +70 c) parameter symbol min. typ. max. unit remark oscillation frequency f osc 160 190 220 khz external resistance: 62 k w frame frequency - 61.7 73.3 84.9 hz external resistance: 62 k w relation between oscillation frequency, frame frequency, and stb frequency the relation between the oscillation frequency, frame frequency, and stb frequency is as follows: 1 frame frequency = 162 x 2 x 8 x oscillation frequency 1 stb frequency = 2 x 8 x oscillation frequency
30 m m m m pd 16662 package drawings standard tcp package ( m pd16662n - 051)(1/3) ?
31 m m m m pd 16662 standard tcp package ( m pd16662n - 051)(2/3) detail of output side test pad and alignment mark 0.3 0.15 0.3 0.15 0.3 0.15 0.95 0.24 0.35 0.35 p0.2 26.5 from pc from pc 16.25 16.25 0.4 0.015 0.6 0.015 detail of cross mark 0.6 0.05 0.05 0.02 0.3 0.05 0.05 0.02 0.6 0.05 0.05 0.02 0.05 0.02 0.6 0.05 right and left center tcp tape winding direction output leads unwinding direction cu pattern is on the backside of the tape winding direction
32 m m m m pd 16662 standard tcp package ( m pd16662n - 051) (3/3) pin connection nc nc nc y1 y2 y3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - y118 y119 y120 nc nc nc nc y121 y122 y123 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - y238 y239 y240 nc nc nc nc v 0 v 1 v 2 gnd v cc1 l1 l2 /dout stb /frm pulse gnd v cc2 ms bmode test /doff rdy /we /oe /cs /ube /reset /refrh pl1 pl0 dir gnd osc2 osc1 v cc2 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd v cc2 gnd v cc1 v 2 v 1 v 0 nc no.1 no.2 no.3 no.4 no.5 no.6 no.7 no.8 no.9 no.10 no.11 no.12 no.13 no.14 no.15 no.16 no.17 no.18 no.19 no.20 no.21 no.22 no.23 no.24 no.25 no.26 no.27 no.28 no.29 no.30 no.31 no.32 no.33 no.34 no.35 no.36 no.37 no.38 no.39 no.40 no.41 no.42 no.43 no.44 no.45 no.46 no.47 no.48 no.49 no.50 no.51 no.52 no.53 no.54 no.55 no.56 no.57 no.58 no.59 no.60 no.61 no.62 no.63 no.64 no.65 no.66 no.67 no.68 no.69 no.70 no.71 no.72 no.73 no.1 no.2 no.3 no.4 no.5 no.6 no.121 no.122 no.123 no.124 no.125 no.126 no.127 no.128 no.129 no.130 no.245 no.246 no.247 no.248 no.249 no.250 die : face down
33 m m m m pd 16662 [memo]
34 m m m m pd 16662 [memo]
35 m m m m pd 16662 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd 16662 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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